Automated test equipment (ATE) includes multiple resources (e.g., analog resources and digital resources for test and measurement) that are applied to a device under test (DUT), such as a die or dies on a semiconductor wafer. The resources are applied through an interface including one or more probe heads, where each probe head includes multiple probe tips to provide an electrical contact to landing pads on the DUT.
Conventional multi-site testing throughput is limited because a total set of one type of ATE resources may be limited to N, where M resources of that type are required to test a die, resulting in the maximum number of dies that may be tested in parallel during each touch-down of the wafer probe being N/M. Further, N/M is an ideal maximum multi-site capability. In practice, the probe card that controls routing to the various probe heads and tips may further constrain the routing density and reduce the amount of possible connections between ATE resources and multiple dies, thereby reducing the attainable multi-site factor.
In addition to the limitations imposed on the multi-site factor by physical constraints, such as available ATE resources and the design of the probe card, heads, and tips, conventional ATE testing is carried out by mapping resources from the ATE onto individual dies on a wafer (or individual packaged parts in final test, where the dies/packaged parts are similarly referred to as DUTs), where all DUTs are tested identically.
That is, a given test executes on all N/M DUTs where, as above, N/M is the multi-site factor (assuming no additional probe card routing constraints). However, the ATE does not necessarily include an equal number of each type of resource. As a result, the multi-site factor is determined by the resource that is least available from the ATE (i.e., the maximum count of the most constrained resource). Examples of such resource limitations include number of analog channels, number of data logging channels, number of high speed interface channels, number of clock channels, and the like. Although higher parallelism is available for ATE resources greater in number, overall test throughput is impeded by the ATE resources that are lower in number, which results in a longer testing time.